1. Field of the Invention
The present invention generally relates to the field of digital electronic circuits, specifically, semiconductor memory devices adapted for use with computer systems. In one aspect, the present invention relates to a semiconductor memory device which has a multi-port function.
2. Description of the Related Art
Generally, a multi-port memory is a memory device having a number of ports for reading and writing and corresponding address and control ports, such that multiple locations in the memory can be simultaneously accessed. A plurality of word lines and a plurality of bit lines are connected to each memory cell of the multi-port memory. Multi-port memories may be used in a variety of applications, such as a cache memory which functions as a memory common to the CPUs incorporated in a multi-CPU system, or as an image memory in which the same address must be accessed at the same time.
With multi-port memories, some ports are dedicated to reading or writing. Alternatively, some of the ports may be used for both reading and writing, though not simultaneously on the same read/write port. With multi-port memories, multiple read and write operations can be performed in a clock cycle. Indeed, a read/write port can be used for both reading and writing when one access is performed in the first half cycle and another access is performed in the second half cycle.
FIG. 1 is a circuit diagram showing a conventional 3-port memory device. In FIG. 1, the first memory node 1 of a memory cell 10, which comprises, for example, a static memory, is connected to a bit line BLa by a transfer gate 14 which is made of an MOS transistor. The gate of the transfer gate 14 is coupled to a word line WLa. The second memory node 2 of the memory cell 10 is connected to a bit line /BLa by a transfer gate 12 which is made of a MOS transistor. The gate of the transfer gate 12 is connected to a word line WLa. The first memory node 1 of the memory cell 10 is also connected to a bit line BLb by a transfer gate 18 which is made of a MOS transistor. The gate of the transfer gate 18 is coupled to a word line WLb. The second memory node 2 of the memory cell 10 is connected to a bit line /BLb by a transfer gate 16 which is made of a MOS transistor. The gate of the transfer gate 16 is coupled to a word line WLb. Further, the first memory node 1 of the memory cell 10 is connected to a bit line BLc by a transfer gate 22 which is made of a MOS transistor. The gate of the transfer gate 22 is coupled to a word line WLc. The second memory node 2 of the memory cell 10 is connected to a bit line /BLc by a transfer gate 20 which is made of a MOS transistor. The gate of the transfer gate 20 is coupled to a word line WLc. As shown, data read from the memory cell 10 may be output directly on a bit line (e.g., BLa), but the data in memory cell 10 may also be inverted by an inverter device (not drawn) before being connected to an output port by an access gate (e.g., transistor 14).
Bit-line load circuits 24, 26, 28 are provided between the bit lines (e.g., load circuit 24 is coupled between bit line BLa and bit line /BLa) for maintaining the potentials of these bit lines at a power-supply potential. Each bit-line load circuit comprises two gate-coupled MOS transistors, each of which has its current path connected, at one end, to a power-supply VDD and, at the other end, to a bit line. Each bit-line load circuit is controlled by a control signal from a bit line control circuit 40 that is provided to the gates of the MOS transistors in the bit-line load circuits 24, 26, 28.
The memory cell 10 stores data values opposite to each other. For example, the memory cell may be implemented as a pair of cross-coupled inverters connected in parallel between first and second memory nodes. Stored data values stored are transferred to the bit lines BLa and /BLa through the transfer gates 14 and 12, in accordance with the potential of the word line WLa. The data values opposite to each other and stored in the memory cell 10 are also transferred to the bit lines BLb and /BLb through the transfer gates 18 and 16, in accordance with the potential of the word line WLb. Further, the data values opposite to each other and stored in the memory cell 10 are also transferred to the bit lines BLc and /BLc through the transfer gates 22 and 20, in accordance with the potential of the word line WLc.
Each port in the memory is identified with respect to the input/output bit line pairs that are used to transfer data into and out of the memory cell. For example, in the three-port memory configuration depicted in FIG. 1, the input/output path using the bit lines BLa and /BLa can be referred to as a first port, the input/output path using the bit lines BLb and /BLb can be referred to as a second port, and the input/output path using the bit lines BLc and /BLc can be referred to as a third port.
As the port number M increases for a multi-port memory, it becomes increasingly difficult to have both stability and writability for the multi-ported cell when non-writing wordlines are activated. For example, where cross-coupled inverters are used for the memory cell, the operation window gets very marginal with conventional three-port memory cells, and can disappear entirely with conventional four-port memory cells. This is because required beta-ratio (which is ratio of the memory cell latch size divided by the access pass-gate size) for cell stability virtually gets M times smaller when not writing.
The diminishing operation margin for cell stability is illustrated in FIGS. 2 and 3, which characterize the stability of the memory cell with the input/output characteristic curves for each inverter of a cross-coupled inverter memory cell in a 3-port memory (FIG. 2) and 4-port memory (FIG. 3). In accordance with conventional techniques for assessing the input/output characteristics of a memory cell, FIG. 2 shows two inverter transfer curves for first and second memory cell inverters. Waveform 50 represents the transfer characteristic (during data reading) for a first inverter in the cross-coupled inverter memory cell (rotated 180 degrees about a diagonal axis) and waveform 60 represents the transfer characteristic for a second inverter in the cross-coupled inverter memory cell. The outer intersection points 52, 56 represent stable points in the circuit operation, but point 54 represents a meta-stable point that is not really stable. As the spread 62, 64 between the curves 50, 60 increases, the stability of the memory device increases, but as the spread 62, 64 decreases, the stability of the memory device decreases.
The stability essentially disappears for a 4-port memory, as illustrated in FIG. 3, which shows inverter transfer waveform 70 (rotated 180 degrees about a diagonal axis) for the first inverter in the cross-coupled inverter memory cell and waveform 80 for the second inverter in the cross-coupled inverter memory cell. As shown in FIG. 3, there is essentially no stability for the 4-port memory device because there is no spread between the waveforms.
Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.